# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.

[options]

# wordswap swaps labels if the pin is on the right side an looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...

wordswap=yes
rotate_labels=yes
#sort_labels=yes
sort_labels=no
generate_pinseq=yes
pinwidthvertical=600
pinwidthhorizontal=600
#sym_width=1400
sym_width=8000

[geda_attr]

# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add

version=20090107 1
name=ATmega644
device=IC
refdes=U?
description=AVR micro 64/2/4 KB
numslots=0
footprint=TQFP44_10
documentation=""
author=Robert Olsson
dist-license=GPL 
use-license=public domain
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=

[pins]

# tabseparated list of pin descriptions
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the Vcc or GND name
# label represents the pinlabel.
#	negation lines can be added with _Q_
#	if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label
#-----------------------------------------------------
# Left


1		io	line	l		PB5 (PCINT13/MOSI)
2		io	line	l		PB6 (PCINT14/MISO)
3		io	line	l		PB7 (PCINT15/SCK)
4		pwr	dot	l	RESET	\_RESET\_
5		pwr	line	l	Vcc	Vcc
6		pwr	none	l 	GND	GND
7		clk	line	l		XTAL2
8		clk	line	l		XTAL1
9		io	line	l		PD0 (PCINT24/RXD0)
10		io	line	l		PD1 (PCINT25/TXD0)
11		io	line	l		PD2 (PCINT26/INT0)
# Bottom
12		io	line	b		PD3 (PCINT27/INT1)
13		io	line	b		PD4 (PCINT28/OC1B)
14		io	line	b		PD5 (PCINT29/OC1A)
15		io	line	b		PD6 (PCINT30/OC2B/ICP)
16		io	line	b		PD7 (PCINT31/OC2A)
17		pwr	line	b	Vcc	Vcc
18		pwr	none	b 	GND	GND
19		io	line	b		PC0 (PCINT16/SCL)
20		io	line	b		PC1 (PCINT17/SDA)
21		io	line	b		PC2 (PCINT18/TCK)
22		io	line	b		PC3 (PCINT19/TMS)

# Right
33		io	line	r		PA4 (ADC4/PCINT4)
32		io	line	r		PA5 (ADC5/PCINT5)
31		io	line	r		PA6 (ADC6/PCINT6)
30		io	line	r		PA7 (ADC7/PCINT7)
29		in	line	r	AREF	AREF
28		pwr	none	r 	GND	GND
27		io	line	r	AVcc	AVcc
26		io	line	r		PC7 (PCINT23/TOSC2)
25		io	line	r		PC6 (PCINT22/TOSC1)
24		io	line	r		PC5 (PCINT21/TDI)
23		io	line	r		PC4 (PCINT20/TDO)

# Top
44		io	line	t		PB4 (PCINT12/OC0B/\_SS\_)
43		io	line	t		PB3 (PCINT11/OC0A/AIN1)
42		io	line	t		PB2 (PCINT10/INT2/AIN0)
41		io	line	t		PB1 (PCINT9/CLKO/T1)
40		io	line	t		PB0 (PCINT8/XCK0/T0)
39		pwr	none	t 	GND	GND
38		pwr	line	t	Vcc	Vcc
37		io	line	t		PA0 (ADC0/PCINT0)
36		io	line	t		PA1 (ADC1/PCINT1)
35		io	line	t		PA2 (ADC2/PCINT2)
34		io	line	t		PA3 (ADC3/PCINT3)