# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.

[options]

# wordswap swaps labels if the pin is on the right side an looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...

wordswap=yes
rotate_labels=yes
#generate_pinseq=yes
pinwidthvertical=500
pinwidthhorizontal=500
sym_width=2800
sort_labels=no

[geda_attr]

# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add

version=20101118 1
name=LPC1768
device=IC
refdes=U1
description=32-bit ARM Cortex-M3 microcontroller Power and Control
numslots=0
footprint=LQFP100_10
documentation=""
author=Siddharth Sharma
dist-license=GPL 
use-license=public domain

[pins]

# tabseparated list of pin descriptions
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the Vcc or GND name
# label represents the pinlabel.
#	negation lines can be added with _Q_
#	if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label
#-----------------------------------------------------
28		pwr	line	l	VDD(3V3)	VDD(3V3)
54		pwr	line	l	VDD(3V3)	VDD(3V3)
71		pwr	line	l	VDD(3V3)	VDD(3V3)
96		pwr	line	l	VDD(3V3)	VDD(3V3)
42		pwr	line	l	VDD(REG)(3V3) 	VDD(REG)(3V3) 
84		pwr	line	l	VDD(REG)(3V3) 	VDD(REG)(3V3) 
10		pwr	line	l	AVDD	AVDD
12		pwr	line	l	VREFP	VREFP
15		pwr	line	l	VREFN	VREFN
19		pwr	line	l	VBAT	VBAT
31		pwr	line	l	GND	GND
41		pwr	line	l	GND	GND
55		pwr	line	l	GND	GND
72		pwr	line	l	GND	GND
83		pwr	line	l	GND	GND
97		pwr	line	l	GND	GND
11		pwr	line	l	AGND	AGND
1		out	line	r		TDO/SWO
2		in	line	r		TDI
3		io	line	r		TMS/SWDIO
4		in	line	r		\_TRST\_
5		clk	line	r		TCK/SWDCLK
100		out	line	r		RTCK
14		out	line	r		\_RSTOUT\_
17		pwr	dot	r	RESET	\_RESET\_
22		clk	clk	r		XTAL1
23		clk	line	r		XTAL2
16		clk	clk	r		RTCX1
18		clk	line	r		RTCX2
13		oc	none	r	NC	NC