v 20101118 1
P 100 19100 400 19100 1 0 0
{
T 300 19150 5 8 1 1 0 6 1
pinnumber=46
T 300 19050 5 8 0 1 0 8 1
pinseq=1
T 450 19100 9 8 1 1 0 0 1
pinlabel=P0[0] (RD1/TXD3/SDA1)
T 450 19100 5 8 0 1 0 2 1
pintype=io
}
P 100 18600 400 18600 1 0 0
{
T 300 18650 5 8 1 1 0 6 1
pinnumber=47
T 300 18550 5 8 0 1 0 8 1
pinseq=2
T 450 18600 9 8 1 1 0 0 1
pinlabel=P0[1] (TD1/RXD3/SCL1)
T 450 18600 5 8 0 1 0 2 1
pintype=io
}
P 100 18100 400 18100 1 0 0
{
T 300 18150 5 8 1 1 0 6 1
pinnumber=98
T 300 18050 5 8 0 1 0 8 1
pinseq=3
T 450 18100 9 8 1 1 0 0 1
pinlabel=P0[2] (TXD0/AD0[7])
T 450 18100 5 8 0 1 0 2 1
pintype=io
}
P 100 17600 400 17600 1 0 0
{
T 300 17650 5 8 1 1 0 6 1
pinnumber=99
T 300 17550 5 8 0 1 0 8 1
pinseq=4
T 450 17600 9 8 1 1 0 0 1
pinlabel=P0[3] (RXD0/AD0[6])
T 450 17600 5 8 0 1 0 2 1
pintype=io
}
P 100 17100 400 17100 1 0 0
{
T 300 17150 5 8 1 1 0 6 1
pinnumber=81
T 300 17050 5 8 0 1 0 8 1
pinseq=5
T 450 17100 9 8 1 1 0 0 1
pinlabel=P0[4] (I2SRXCLK/RD2/CAP2[0])
T 450 17100 5 8 0 1 0 2 1
pintype=io
}
P 100 16600 400 16600 1 0 0
{
T 300 16650 5 8 1 1 0 6 1
pinnumber=80
T 300 16550 5 8 0 1 0 8 1
pinseq=6
T 450 16600 9 8 1 1 0 0 1
pinlabel=P0[5] (I2SRXWS/TD2/CAP2[1])
T 450 16600 5 8 0 1 0 2 1
pintype=io
}
P 100 16100 400 16100 1 0 0
{
T 300 16150 5 8 1 1 0 6 1
pinnumber=79
T 300 16050 5 8 0 1 0 8 1
pinseq=7
T 450 16100 9 8 1 1 0 0 1
pinlabel=P0[6] (I2SRXSDA/SSEL1/MAT2[0])
T 450 16100 5 8 0 1 0 2 1
pintype=io
}
P 100 15600 400 15600 1 0 0
{
T 300 15650 5 8 1 1 0 6 1
pinnumber=78
T 300 15550 5 8 0 1 0 8 1
pinseq=8
T 450 15600 9 8 1 1 0 0 1
pinlabel=P0[7] (I2STXCLK/SCK1/MAT2[1])
T 450 15600 5 8 0 1 0 2 1
pintype=io
}
P 100 15100 400 15100 1 0 0
{
T 300 15150 5 8 1 1 0 6 1
pinnumber=77
T 300 15050 5 8 0 1 0 8 1
pinseq=9
T 450 15100 9 8 1 1 0 0 1
pinlabel=P0[8] (I2STXWS/MISO1/MAT2[2])
T 450 15100 5 8 0 1 0 2 1
pintype=io
}
P 100 14600 400 14600 1 0 0
{
T 300 14650 5 8 1 1 0 6 1
pinnumber=76
T 300 14550 5 8 0 1 0 8 1
pinseq=10
T 450 14600 9 8 1 1 0 0 1
pinlabel=P0[9] (I2STXSDA/MOSI1/MAT2[3])
T 450 14600 5 8 0 1 0 2 1
pintype=io
}
P 100 14100 400 14100 1 0 0
{
T 300 14150 5 8 1 1 0 6 1
pinnumber=48
T 300 14050 5 8 0 1 0 8 1
pinseq=11
T 450 14100 9 8 1 1 0 0 1
pinlabel=P0[10] (TXD2/SDA2/MAT3[0])
T 450 14100 5 8 0 1 0 2 1
pintype=io
}
P 100 13600 400 13600 1 0 0
{
T 300 13650 5 8 1 1 0 6 1
pinnumber=49
T 300 13550 5 8 0 1 0 8 1
pinseq=12
T 450 13600 9 8 1 1 0 0 1
pinlabel=P0[11] (RXD2/SCL2/MAT3[1])
T 450 13600 5 8 0 1 0 2 1
pintype=io
}
P 100 13100 400 13100 1 0 0
{
T 300 13150 5 8 1 1 0 6 1
pinnumber=62
T 300 13050 5 8 0 1 0 8 1
pinseq=13
T 450 13100 9 8 1 1 0 0 1
pinlabel=P0[15] (TXD1/SCK0/SCK)
T 450 13100 5 8 0 1 0 2 1
pintype=io
}
P 100 12600 400 12600 1 0 0
{
T 300 12650 5 8 1 1 0 6 1
pinnumber=63
T 300 12550 5 8 0 1 0 8 1
pinseq=14
T 450 12600 9 8 1 1 0 0 1
pinlabel=P0[16] (RXD1/SSEL0/SSEL)
T 450 12600 5 8 0 1 0 2 1
pintype=io
}
P 100 12100 400 12100 1 0 0
{
T 300 12150 5 8 1 1 0 6 1
pinnumber=61
T 300 12050 5 8 0 1 0 8 1
pinseq=15
T 450 12100 9 8 1 1 0 0 1
pinlabel=P0[17] (CTS1/MISO0/MISO)
T 450 12100 5 8 0 1 0 2 1
pintype=io
}
P 100 11600 400 11600 1 0 0
{
T 300 11650 5 8 1 1 0 6 1
pinnumber=60
T 300 11550 5 8 0 1 0 8 1
pinseq=16
T 450 11600 9 8 1 1 0 0 1
pinlabel=P0[18] (DCD1/MOSI0/MOSI)
T 450 11600 5 8 0 1 0 2 1
pintype=io
}
P 100 11100 400 11100 1 0 0
{
T 300 11150 5 8 1 1 0 6 1
pinnumber=59
T 300 11050 5 8 0 1 0 8 1
pinseq=17
T 450 11100 9 8 1 1 0 0 1
pinlabel=P0[19] (DSR1/SDA1)
T 450 11100 5 8 0 1 0 2 1
pintype=io
}
P 100 10600 400 10600 1 0 0
{
T 300 10650 5 8 1 1 0 6 1
pinnumber=58
T 300 10550 5 8 0 1 0 8 1
pinseq=18
T 450 10600 9 8 1 1 0 0 1
pinlabel=P0[20] (DTR1/SCL1)
T 450 10600 5 8 0 1 0 2 1
pintype=io
}
P 100 10100 400 10100 1 0 0
{
T 300 10150 5 8 1 1 0 6 1
pinnumber=57
T 300 10050 5 8 0 1 0 8 1
pinseq=19
T 450 10100 9 8 1 1 0 0 1
pinlabel=P0[21] (RI1/RD1)
T 450 10100 5 8 0 1 0 2 1
pintype=io
}
P 100 9600 400 9600 1 0 0
{
T 300 9650 5 8 1 1 0 6 1
pinnumber=56
T 300 9550 5 8 0 1 0 8 1
pinseq=20
T 450 9600 9 8 1 1 0 0 1
pinlabel=P0[22] (RTS1/TD1)
T 450 9600 5 8 0 1 0 2 1
pintype=io
}
P 100 9100 400 9100 1 0 0
{
T 300 9150 5 8 1 1 0 6 1
pinnumber=9
T 300 9050 5 8 0 1 0 8 1
pinseq=21
T 450 9100 9 8 1 1 0 0 1
pinlabel=P0[23] (AD0[0]/I2SRXCLK/CAP3[0])
T 450 9100 5 8 0 1 0 2 1
pintype=io
}
P 100 8600 400 8600 1 0 0
{
T 300 8650 5 8 1 1 0 6 1
pinnumber=8
T 300 8550 5 8 0 1 0 8 1
pinseq=22
T 450 8600 9 8 1 1 0 0 1
pinlabel=P0[24] (AD0[1]/I2SRXWS/CAP3[1])
T 450 8600 5 8 0 1 0 2 1
pintype=io
}
P 100 8100 400 8100 1 0 0
{
T 300 8150 5 8 1 1 0 6 1
pinnumber=7
T 300 8050 5 8 0 1 0 8 1
pinseq=23
T 450 8100 9 8 1 1 0 0 1
pinlabel=P0[25] (AD0[2]/I2SRXSDA/TXD3)
T 450 8100 5 8 0 1 0 2 1
pintype=io
}
P 100 7600 400 7600 1 0 0
{
T 300 7650 5 8 1 1 0 6 1
pinnumber=6
T 300 7550 5 8 0 1 0 8 1
pinseq=24
T 450 7600 9 8 1 1 0 0 1
pinlabel=P0[26] (AD0[3]/AOUT/RXD3)
T 450 7600 5 8 0 1 0 2 1
pintype=io
}
P 100 7100 400 7100 1 0 0
{
T 300 7150 5 8 1 1 0 6 1
pinnumber=25
T 300 7050 5 8 0 1 0 8 1
pinseq=25
T 450 7100 9 8 1 1 0 0 1
pinlabel=P0[27] (SDA0/USBSDA)
T 450 7100 5 8 0 1 0 2 1
pintype=io
}
P 100 6600 400 6600 1 0 0
{
T 300 6650 5 8 1 1 0 6 1
pinnumber=24
T 300 6550 5 8 0 1 0 8 1
pinseq=26
T 450 6600 9 8 1 1 0 0 1
pinlabel=P0[28] (SCL0/USBSCL)
T 450 6600 5 8 0 1 0 2 1
pintype=io
}
P 100 6100 400 6100 1 0 0
{
T 300 6150 5 8 1 1 0 6 1
pinnumber=29
T 300 6050 5 8 0 1 0 8 1
pinseq=27
T 450 6100 9 8 1 1 0 0 1
pinlabel=P0[29] (USBD+)
T 450 6100 5 8 0 1 0 2 1
pintype=io
}
P 100 5600 400 5600 1 0 0
{
T 300 5650 5 8 1 1 0 6 1
pinnumber=30
T 300 5550 5 8 0 1 0 8 1
pinseq=28
T 450 5600 9 8 1 1 0 0 1
pinlabel=P0[30] (USBD−)
T 450 5600 5 8 0 1 0 2 1
pintype=io
}
P 6700 19100 6400 19100 1 0 0
{
T 6500 19150 5 8 1 1 0 0 1
pinnumber=95
T 6500 19050 5 8 0 1 0 2 1
pinseq=29
T 6350 19100 9 8 1 1 0 6 1
pinlabel=(ENETTXD0) P1[0]
T 6350 19100 5 8 0 1 0 8 1
pintype=io
}
P 6700 18600 6400 18600 1 0 0
{
T 6500 18650 5 8 1 1 0 0 1
pinnumber=94
T 6500 18550 5 8 0 1 0 2 1
pinseq=30
T 6350 18600 9 8 1 1 0 6 1
pinlabel=(ENETTXD1) P1[1]
T 6350 18600 5 8 0 1 0 8 1
pintype=io
}
P 6700 18100 6400 18100 1 0 0
{
T 6500 18150 5 8 1 1 0 0 1
pinnumber=93
T 6500 18050 5 8 0 1 0 2 1
pinseq=31
T 6350 18100 9 8 1 1 0 6 1
pinlabel=(ENETTXEN) P1[4]
T 6350 18100 5 8 0 1 0 8 1
pintype=io
}
P 6700 17600 6400 17600 1 0 0
{
T 6500 17650 5 8 1 1 0 0 1
pinnumber=92
T 6500 17550 5 8 0 1 0 2 1
pinseq=32
T 6350 17600 9 8 1 1 0 6 1
pinlabel=(ENETCRS) P1[8]
T 6350 17600 5 8 0 1 0 8 1
pintype=io
}
P 6700 17100 6400 17100 1 0 0
{
T 6500 17150 5 8 1 1 0 0 1
pinnumber=91
T 6500 17050 5 8 0 1 0 2 1
pinseq=33
T 6350 17100 9 8 1 1 0 6 1
pinlabel=(ENETRXD0) P1[9]
T 6350 17100 5 8 0 1 0 8 1
pintype=io
}
P 6700 16600 6400 16600 1 0 0
{
T 6500 16650 5 8 1 1 0 0 1
pinnumber=90
T 6500 16550 5 8 0 1 0 2 1
pinseq=34
T 6350 16600 9 8 1 1 0 6 1
pinlabel=(ENETRXD1) P1[10]
T 6350 16600 5 8 0 1 0 8 1
pintype=io
}
P 6700 16100 6400 16100 1 0 0
{
T 6500 16150 5 8 1 1 0 0 1
pinnumber=89
T 6500 16050 5 8 0 1 0 2 1
pinseq=35
T 6350 16100 9 8 1 1 0 6 1
pinlabel=(ENETRXER) P1[14]
T 6350 16100 5 8 0 1 0 8 1
pintype=io
}
P 6700 15600 6400 15600 1 0 0
{
T 6500 15650 5 8 1 1 0 0 1
pinnumber=88
T 6500 15550 5 8 0 1 0 2 1
pinseq=36
T 6350 15600 9 8 1 1 0 6 1
pinlabel=(ENETREFCLK) P1[15]
T 6350 15600 5 8 0 1 0 8 1
pintype=io
}
P 6700 15100 6400 15100 1 0 0
{
T 6500 15150 5 8 1 1 0 0 1
pinnumber=87
T 6500 15050 5 8 0 1 0 2 1
pinseq=37
T 6350 15100 9 8 1 1 0 6 1
pinlabel=(ENETMDC) P1[16]
T 6350 15100 5 8 0 1 0 8 1
pintype=io
}
P 6700 14600 6400 14600 1 0 0
{
T 6500 14650 5 8 1 1 0 0 1
pinnumber=86
T 6500 14550 5 8 0 1 0 2 1
pinseq=38
T 6350 14600 9 8 1 1 0 6 1
pinlabel=(ENETMDIO) P1[17]
T 6350 14600 5 8 0 1 0 8 1
pintype=io
}
P 6700 14100 6400 14100 1 0 0
{
T 6500 14150 5 8 1 1 0 0 1
pinnumber=32
T 6500 14050 5 8 0 1 0 2 1
pinseq=39
T 6350 14100 9 8 1 1 0 6 1
pinlabel=(USBUPLED/PWM1[1]/CAP1[0]) P1[18]
T 6350 14100 5 8 0 1 0 8 1
pintype=io
}
P 6700 13600 6400 13600 1 0 0
{
T 6500 13650 5 8 1 1 0 0 1
pinnumber=33
T 6500 13550 5 8 0 1 0 2 1
pinseq=40
T 6350 13600 9 8 1 1 0 6 1
pinlabel=(MCOA0/\_USBPPWR\_/CAP1[1]) P1[19]
T 6350 13600 5 8 0 1 0 8 1
pintype=io
}
P 6700 13100 6400 13100 1 0 0
{
T 6500 13150 5 8 1 1 0 0 1
pinnumber=34
T 6500 13050 5 8 0 1 0 2 1
pinseq=41
T 6350 13100 9 8 1 1 0 6 1
pinlabel=(MCI0/PWM1[2]/SCK0) P1[20]
T 6350 13100 5 8 0 1 0 8 1
pintype=io
}
P 6700 12600 6400 12600 1 0 0
{
T 6500 12650 5 8 1 1 0 0 1
pinnumber=35
T 6500 12550 5 8 0 1 0 2 1
pinseq=42
T 6350 12600 9 8 1 1 0 6 1
pinlabel=(\_MCABORT\_/PWM1[3]/SSEL0) P1[21]
T 6350 12600 5 8 0 1 0 8 1
pintype=io
}
P 6700 12100 6400 12100 1 0 0
{
T 6500 12150 5 8 1 1 0 0 1
pinnumber=36
T 6500 12050 5 8 0 1 0 2 1
pinseq=43
T 6350 12100 9 8 1 1 0 6 1
pinlabel=(MCOB0/USBPWRD/MAT1[0]) P1[22]
T 6350 12100 5 8 0 1 0 8 1
pintype=io
}
P 6700 11600 6400 11600 1 0 0
{
T 6500 11650 5 8 1 1 0 0 1
pinnumber=37
T 6500 11550 5 8 0 1 0 2 1
pinseq=44
T 6350 11600 9 8 1 1 0 6 1
pinlabel=(MCI1/PWM1[4]/MISO0) P1[23]
T 6350 11600 5 8 0 1 0 8 1
pintype=io
}
P 6700 11100 6400 11100 1 0 0
{
T 6500 11150 5 8 1 1 0 0 1
pinnumber=38
T 6500 11050 5 8 0 1 0 2 1
pinseq=45
T 6350 11100 9 8 1 1 0 6 1
pinlabel=(MCI2/PWM1[5]/MOSI0) P1[24]
T 6350 11100 5 8 0 1 0 8 1
pintype=io
}
P 6700 10600 6400 10600 1 0 0
{
T 6500 10650 5 8 1 1 0 0 1
pinnumber=39
T 6500 10550 5 8 0 1 0 2 1
pinseq=46
T 6350 10600 9 8 1 1 0 6 1
pinlabel=(MCOA1/MAT1[1]) P1[25]
T 6350 10600 5 8 0 1 0 8 1
pintype=io
}
P 6700 10100 6400 10100 1 0 0
{
T 6500 10150 5 8 1 1 0 0 1
pinnumber=40
T 6500 10050 5 8 0 1 0 2 1
pinseq=47
T 6350 10100 9 8 1 1 0 6 1
pinlabel=(MCOB1/PWM1[6]/CAP0[0]) P1[26]
T 6350 10100 5 8 0 1 0 8 1
pintype=io
}
P 6700 9600 6400 9600 1 0 0
{
T 6500 9650 5 8 1 1 0 0 1
pinnumber=43
T 6500 9550 5 8 0 1 0 2 1
pinseq=48
T 6350 9600 9 8 1 1 0 6 1
pinlabel=(CLKOUT/\_USBOVRCR\_/CAP0[1]) P1[27]
T 6350 9600 5 8 0 1 0 8 1
pintype=io
}
P 6700 9100 6400 9100 1 0 0
{
T 6500 9150 5 8 1 1 0 0 1
pinnumber=44
T 6500 9050 5 8 0 1 0 2 1
pinseq=49
T 6350 9100 9 8 1 1 0 6 1
pinlabel=(MCOA2/PCAP1[0]/MAT0[0]) P1[28]
T 6350 9100 5 8 0 1 0 8 1
pintype=io
}
P 6700 8600 6400 8600 1 0 0
{
T 6500 8650 5 8 1 1 0 0 1
pinnumber=45
T 6500 8550 5 8 0 1 0 2 1
pinseq=50
T 6350 8600 9 8 1 1 0 6 1
pinlabel=(MCOB2/PCAP1[1]/MAT0[1]) P1[29]
T 6350 8600 5 8 0 1 0 8 1
pintype=io
}
P 6700 8100 6400 8100 1 0 0
{
T 6500 8150 5 8 1 1 0 0 1
pinnumber=21
T 6500 8050 5 8 0 1 0 2 1
pinseq=51
T 6350 8100 9 8 1 1 0 6 1
pinlabel=(VBUS/AD0[4]) P1[30]
T 6350 8100 5 8 0 1 0 8 1
pintype=io
}
P 6700 7600 6400 7600 1 0 0
{
T 6500 7650 5 8 1 1 0 0 1
pinnumber=20
T 6500 7550 5 8 0 1 0 2 1
pinseq=52
T 6350 7600 9 8 1 1 0 6 1
pinlabel=(SCK1/AD0[5]) P1[31]
T 6350 7600 5 8 0 1 0 8 1
pintype=io
}
P 6700 7100 6400 7100 1 0 0
{
T 6500 7150 5 8 1 1 0 0 1
pinnumber=75
T 6500 7050 5 8 0 1 0 2 1
pinseq=53
T 6350 7100 9 8 1 1 0 6 1
pinlabel=(PWM1[1]/TXD1) P2[0]
T 6350 7100 5 8 0 1 0 8 1
pintype=io
}
P 6700 6600 6400 6600 1 0 0
{
T 6500 6650 5 8 1 1 0 0 1
pinnumber=74
T 6500 6550 5 8 0 1 0 2 1
pinseq=54
T 6350 6600 9 8 1 1 0 6 1
pinlabel=(PWM1[2]/RXD1) P2[1]
T 6350 6600 5 8 0 1 0 8 1
pintype=io
}
P 6700 6100 6400 6100 1 0 0
{
T 6500 6150 5 8 1 1 0 0 1
pinnumber=73
T 6500 6050 5 8 0 1 0 2 1
pinseq=55
T 6350 6100 9 8 1 1 0 6 1
pinlabel=(PWM1[3]/CTS1/TRACEDATA[3]) P2[2]
T 6350 6100 5 8 0 1 0 8 1
pintype=io
}
P 6700 5600 6400 5600 1 0 0
{
T 6500 5650 5 8 1 1 0 0 1
pinnumber=70
T 6500 5550 5 8 0 1 0 2 1
pinseq=56
T 6350 5600 9 8 1 1 0 6 1
pinlabel=(PWM1[4]/DCD1/TRACEDATA[2]) P2[3]
T 6350 5600 5 8 0 1 0 8 1
pintype=io
}
P 6700 5100 6400 5100 1 0 0
{
T 6500 5150 5 8 1 1 0 0 1
pinnumber=69
T 6500 5050 5 8 0 1 0 2 1
pinseq=57
T 6350 5100 9 8 1 1 0 6 1
pinlabel=(PWM1[5]/DSR1/TRACEDATA[1]) P2[4]
T 6350 5100 5 8 0 1 0 8 1
pintype=io
}
P 6700 4600 6400 4600 1 0 0
{
T 6500 4650 5 8 1 1 0 0 1
pinnumber=68
T 6500 4550 5 8 0 1 0 2 1
pinseq=58
T 6350 4600 9 8 1 1 0 6 1
pinlabel=(PWM1[6]/DTR1/TRACEDATA[0]) P2[5]
T 6350 4600 5 8 0 1 0 8 1
pintype=io
}
P 6700 4100 6400 4100 1 0 0
{
T 6500 4150 5 8 1 1 0 0 1
pinnumber=67
T 6500 4050 5 8 0 1 0 2 1
pinseq=59
T 6350 4100 9 8 1 1 0 6 1
pinlabel=(PCAP1[0]/RI1/TRACECLK) P2[6]
T 6350 4100 5 8 0 1 0 8 1
pintype=io
}
P 6700 3600 6400 3600 1 0 0
{
T 6500 3650 5 8 1 1 0 0 1
pinnumber=66
T 6500 3550 5 8 0 1 0 2 1
pinseq=60
T 6350 3600 9 8 1 1 0 6 1
pinlabel=(RD2/RTS1) P2[7]
T 6350 3600 5 8 0 1 0 8 1
pintype=io
}
P 6700 3100 6400 3100 1 0 0
{
T 6500 3150 5 8 1 1 0 0 1
pinnumber=65
T 6500 3050 5 8 0 1 0 2 1
pinseq=61
T 6350 3100 9 8 1 1 0 6 1
pinlabel=(TD2/TXD2) P2[8]
T 6350 3100 5 8 0 1 0 8 1
pintype=io
}
P 6700 2600 6400 2600 1 0 0
{
T 6500 2650 5 8 1 1 0 0 1
pinnumber=64
T 6500 2550 5 8 0 1 0 2 1
pinseq=62
T 6350 2600 9 8 1 1 0 6 1
pinlabel=(USBCONNECT/RXD2) P2[9]
T 6350 2600 5 8 0 1 0 8 1
pintype=io
}
P 6700 2100 6400 2100 1 0 0
{
T 6500 2150 5 8 1 1 0 0 1
pinnumber=53
T 6500 2050 5 8 0 1 0 2 1
pinseq=63
T 6350 2100 9 8 1 1 0 6 1
pinlabel=(\_EINT0\_/NMI) P2[10]
T 6350 2100 5 8 0 1 0 8 1
pintype=io
}
P 6700 1600 6400 1600 1 0 0
{
T 6500 1650 5 8 1 1 0 0 1
pinnumber=52
T 6500 1550 5 8 0 1 0 2 1
pinseq=64
T 6350 1600 9 8 1 1 0 6 1
pinlabel=(\_EINT1\_/I2STXCLK) P2[11]
T 6350 1600 5 8 0 1 0 8 1
pintype=io
}
P 6700 1100 6400 1100 1 0 0
{
T 6500 1150 5 8 1 1 0 0 1
pinnumber=51
T 6500 1050 5 8 0 1 0 2 1
pinseq=65
T 6350 1100 9 8 1 1 0 6 1
pinlabel=(\_EINT2\_/I2STXWS) P2[12]
T 6350 1100 5 8 0 1 0 8 1
pintype=io
}
P 6700 600 6400 600 1 0 0
{
T 6500 650 5 8 1 1 0 0 1
pinnumber=50
T 6500 550 5 8 0 1 0 2 1
pinseq=66
T 6350 600 9 8 1 1 0 6 1
pinlabel=(\_EINT3\_/I2STXSDA) P2[13]
T 6350 600 5 8 0 1 0 8 1
pintype=io
}
P 100 5100 400 5100 1 0 0
{
T 300 5150 5 8 1 1 0 6 1
pinnumber=27
T 300 5050 5 8 0 1 0 8 1
pinseq=67
T 450 5100 9 8 1 1 0 0 1
pinlabel=P3[25] (MAT0[0]/PWM1[2])
T 450 5100 5 8 0 1 0 2 1
pintype=io
}
P 100 4600 400 4600 1 0 0
{
T 300 4650 5 8 1 1 0 6 1
pinnumber=26
T 300 4550 5 8 0 1 0 8 1
pinseq=68
T 450 4600 9 8 1 1 0 0 1
pinlabel=P3[26] (STCLK/MAT0[1]/PWM1[3])
T 450 4600 5 8 0 1 0 2 1
pintype=io
}
P 100 4100 400 4100 1 0 0
{
T 300 4150 5 8 1 1 0 6 1
pinnumber=82
T 300 4050 5 8 0 1 0 8 1
pinseq=69
T 450 4100 9 8 1 1 0 0 1
pinlabel=P4[28] (RXMCLK/MAT2[0]/TXD3)
T 450 4100 5 8 0 1 0 2 1
pintype=io
}
P 100 3600 400 3600 1 0 0
{
T 300 3650 5 8 1 1 0 6 1
pinnumber=85
T 300 3550 5 8 0 1 0 8 1
pinseq=70
T 450 3600 9 8 1 1 0 0 1
pinlabel=P4[29] (TXMCLK/MAT2[1]/RXD3)
T 450 3600 5 8 0 1 0 2 1
pintype=io
}
B 400 100 6000 19500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 6400 19700 8 10 1 1 0 6 1
refdes=U1
T 400 19700 9 10 1 0 0 0 1
LPC1768
T 400 19900 5 10 0 0 0 0 1
device=IC
T 400 20100 5 10 0 0 0 0 1
footprint=LQFP100_10
T 400 20300 5 10 0 0 0 0 1
author=Siddharth Sharma
T 400 20500 5 10 0 0 0 0 1
documentation=""
T 400 20700 5 10 0 0 0 0 1
description=32-bit ARM Cortex-M3 microcontroller GPIOs
T 400 20900 5 10 0 0 0 0 1
numslots=0
T 400 21100 5 10 0 0 0 0 1
dist-license=GPL
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